 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TC2997G PRE2_20071107 Preliminary 3.5 GHz 16 W Flange Ceramic Packaged GaAs Power FETs FEATURES 16 W Typical Power at 3.5 GHz 9 dB Typical Linear Power Gain at 3.5 GHz High Linearity: IP3 = 52 dBm Typical High Power Added Efficiency: Nominal PAE of 37 % 100 % DC and RF Tested Flange Ceramic Package Suitable for WiMax and WLL applications PHOTO ENLARGEMENT DESCRIPTION The TC2997G is a packaged Pseudomorphic High Electron Mobility Transistor (PHEMT) power transistor. The flange ceramic package provides the best thermal conductivity for the GaAs FET. All devices are 100% DC and RF tested to assure consistent quality. Typical applications include high dynamic range power amplifier for commercial applications. ELECTRICAL SPECIFICATIONS Symbol P1dB GL IP3 PAE IDSS gm VP BVDGO Rth CONDITIONS Output Power at 1dB Gain Compression Point, Vd = 10V, Id = 4A, f=3.4 - 3.6GHz Linear Power Gain Vd = 10V, Id = 4A, f=3.4 - 3.6GHz Intercept Point of the 3 -order Intermodulation, Vd = 10V, Id = 4A, f=3.4 - 3.6GHz, *PSCL = 32 dBm rd MIN 41.5 8 TYP 42.5 9 52 37 18.75 13500 -1.7 MAX UNIT dBm dB dBm % A mS Volts Volts C/W Power Added Efficiency at 1dB Compression Power Saturated Drain-Source Current at VDS = 2 V, VGS = 0 V Transconductance at VDS = 2 V, VGS = 0 V Pinch-off Voltage at VDS = 2 V, ID = 60 mA Drain-Gate Breakdown Voltage at IDGO =15 mA Thermal Resistance 20 22 0.6 *PSCL: Output Power of Single Carrier Level, delta frequency=5MHz. ABSOLUTE MAXIMUM RATINGS at 25 C Symbol VDS VGS IDS Pin PT TCH TSTG Parameter Drain-Source Voltage Gate-Source Voltage Drain Current RF Input Power, CW Continuous Dissipation Channel Temperature Storage Temperature Rating 12 V -5 V IDSS 37.5 dBm 150 W 175 C - 65 C to +175 C HANDLING PRECAUTIONS: The user must operate in a clean, dry environment. Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. The static discharge must be less than 300V. TRANSCOM, INC., 90 Dasoong 7th Road, Tainan Science-Based Industrial Park, Shanhua Jen, Tainan County, Taiwan Web-Site: www.transcominc.com.tw Phone: 886-6-5050086 Fax: 886-6-5051602 P1/3 TC2997G PRE2_20071107 FLANGE PACKAGE OUTLINE (in mm) Gate Source Source Drain EVALUATION BOARD Rg5, 100ohm Rg6, 100ohm Co4, 1000pF Rg4, 1Kohm VR1, 1Kohm Rg7, Thermistor 100ohm Co5, 0.1uF Co6, 10uF PCB Material: RO4003 ER = 3.38 Thickness = 20 mil Unit: mil Rg3, 0ohm Q1, FMMT2907A Ci5, 10uF Rg2, 1Kohm Ci4, 0.1uF Ci3, 1000pF Rg1, 10ohm Ci1, ATC600B 1.5 pF Vg=-5V Vd=10V Vg Vd 0805 Co1, ATC600B 0.4 pF 0805 0805 Co3, ATC600B 2 pF 0805 0805 Ci2, ATC600B 0.2 pF RF in 386-350031 -001 Unit: mil RF out T9X_ 3.3~3.8GHz Co2, ATC600B 0.7 pF TRANSCOM, INC., 90 Dasoong 7th Road, Tainan Science-Based Industrial Park, Shanhua Jen, Tainan County, Taiwan Web-Site: www.transcominc.com.tw Phone: 886-6-5050086 Fax: 886-6-5051602 P2/3 TC2997G PRE2_20071107 Evaluation Board Parts List Qt'y 1 2 1 2 1 1 1 2 2 2 1 1 1 1 1 Description Chip resistor (1206) 105% Chip resistor (0603) 1K5% Chip resistor (0603) 05% Chip resistor (0603) 1005% Thermistor (0402) 100 5% SMT Trimmer Potentiometers (3.0*3.0mm) 1K PNP, FMMT2907A (SOT-23) Chip CAP (0603) 1000PF10% Chip CAP (0603) 0.1F20% Chip CAP (1210) 10F20% or (1206) 10F20%) Chip CAP (0805) 1.5PF0.1PF Chip CAP (0805) 0.2PF0.1PF Chip CAP (0805) 0.4PF0.1PF Chip CAP (0805) 0.7PF0.1PF Chip CAP (0805) 2PF0.1PF Reference Designator Rg1 Rg2, Rg4 Rg3 Rg5, Rg6 Rg7 VR1 Q1 Ci3, Co4 Ci4, Co5 Ci5, Co6 Ci1 Ci2 Co1 Co2 Co3 Manufacturer Inventory ID Murata Murata Murata American Technical Ceramics American Technical Ceramics American Technical Ceramics American Technical Ceramics American Technical Ceramics GRM39X7R102K50V GRM39Y5V104Z25V GRM42-6Y5V106Z25V or GRM31CF5E106ZA01L ATC 600F1R5BT250 WVDC ATC 600F0R2BT250 WVDC ATC 600F0R4BT250 WVDC ATC 600F0R7BT250 WVDC ATC 600F2R0BT250 WVDC Application Note: High power FET turn on procedure For evaluating or operating the high power FET, following turn-on and turn-off procedures are highly recommended to avoid the device oscillations or burnout. Turn-on Procedure: 1.The input and output of the device must connect to 50ohm. 2.ESD protection. 3.Vd must connect to external "Regulated Circuit" with a DC regulator included, as similar as the idea shown herewith. 4.Voltage spike protection on input and output DC biasing is recommended. 5.Vgs set to -3V. 6.Open the output DC biasing (Vds). 7.Increase Vgs to get Idsq, quiescent drain current. 8.Turn on the RF driver. Turn-off Procedure: 1.Turn off the RF driver. 2.Vg set to -3V. 3.Turn off Vd. 4.Turn off Vg. TRANSCOM, INC., 90 Dasoong 7th Road, Tainan Science-Based Industrial Park, Shanhua Jen, Tainan County, Taiwan, R.O.C. Web-Site: www.transcominc.com.tw Phone: 886-6-5050086 Fax: 886-6-5051602 P3/3 |
Price & Availability of TC2997G
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |